Design of a Compact, Low Inductance 1200 V, 6.5 mΩ SiC Half-Bridge Power Module with Flexible PCB Gate Loop Connection

2019 IEEE Applied Power Electronics Conference and Exposition (APEC)(2019)

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摘要
This paper describes the design, packaging and test setup of a compact, low inductance, 1200 V, 6.5 mΩ half-bridge power module. In the design of this power module, the use of new techniques advances the properties of a SiC power module. The design has a power loop inductance of 3.9 nH and a gate loop inductance of 0.3 nH determined by Ansys Q3D. The low gate loop inductance is achieved with the use of a flexible gate circuit to connect to the gate and source of the die as well as a desaturation test point. Lastly, the use of the MOSFET body diode in place of an antiparallel external diode allows for a compact layout. The design of a symmetrical layout and the fabrication of the power module is described. Two power modules are designed to compare current sharing behavior, the control sample with balanced die, the other sample with unbalanced die. A clamped inductive load tester set-up is designed to interface uniquely with the flexible PCB pins and the leads of the module. Use of Rogowski coils can allow for analysis of the individual die currents to determine the effects of unbalanced die on the power module performance.
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关键词
Inductance,Multichip modules,Logic gates,Silicon carbide,Substrates,Wires,Copper
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