A Low-Power Sipm Readout Front-End With Fast Pulse Generation And Successive-Approximation Register Adc In 0.18 Mu M Cmos

This paper presents a low-power silicon photomultiplier (SiPM) readout front-end with on-chip fast pulse generation and successive-approximation-register (SAR) ADC. The front-end mainly consists of a current buffer with an on-chip C-R high pass filter (HPF), a charge integrator, a current discriminator, and a 10-bit low-power SAR ADC. The current-mode buffer offers a low input impedance thus achieving a high input bandwidth. The on-chip HPF shortens the width of the SiPM's long-tailed single photo-electron (SPE) response to generate the fast pulse signal, which allows the current discriminator to suppress the uncertainty of timing measurement and helps to achieve a better coincidence resolving time (CRT). Compared with off-chip fast pulse generators, no additional I/O pin is required facilitating compact multi-channel SiPM readouts. By reusing the charge integration capacitor as the sampling capacitor of the SAR ADC, the power-hungry charge sensitive amplifier (CSA) is eliminated. The front-end is designed in a 0.18 pm 1P6M standard CMOS technology, and has a low power consumption of 4 mW. The on-chip HPF reshapes the long-tailed SPE pulse width from 50 ns to 3 ns. At 1 MS/s, the SAR ADC consumes 132 mu W from a 1.8 V supply, and achieves a SNDR of 58.11 dB and a SFDR of 72.47 dB, respectively.