A 12-Bit 30ms/S Sar Adc With Vco-Based Comparator And Split-And-Recombination Redundancy For Bypass Logic

This paper presents a 12-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) implemented in 40nm CMOS technology. A VCO-based comparator is employed to adjust the noise level adaptively and its oscillation number is harnessed to bypass unnecessary cycles for saving energy. A 1-bit split-and-recombination redundancy and a digital error correction for bypass logic are proposed to address the settling issues and refine the bypass window size. The sampling speed of the ADC reaches up to 30MS/s, which is the highest among SAR ADCs with single time-domain comparator. The ADC achieves an SFDR of 85.35 dB and 11.12-bit ENOB with Nyquist input consuming 0.38mW at a 1.1V supply, resulting in a figure of merit (FoM) of 5.69 fJ/conversion-step.