Compact Design Of High-Speed Low-Error Four-Quadrant Current Multiplier With Reduced Power Dissipation

In this paper, a compact low-power, high-speed, low-error four-quadrant analog multiplier is proposed using a new simple current squarer circuit. The new squarer circuit consists of an NMOS transistor, which operates in saturation region, plus a resistor. The proposed multiplier has a balanced structure composed of four squarer cells and a simple current mirror. This multiplier also has the important property of not using bias currents which results in greatly reduced power. The performance of the proposed design (for passive and active realization of the resistors) has been simulated using HSPICE software in 0.18 mu m TSMC (level-49) CMOS technology. Simulation results with +/- 0.7-V DC supply voltages show (for passive realization) that the maximum linearity error is 0.35%, the -3dB bandwidth (BW) is 903MHz, the total harmonic distortion (THD) is 0.3% (at 1MHz), and the maximum and static power consumption are 139.25 mu W and 14.5 mu W, respectively. Also, post-layout simulation results are extracted, which give the maximum linearity error as 0.4%, the -3dB BW as 657MHz and the THD as 0.35%, as well. Moreover, Monte Carlo analysis are performed to verify the satisfactory robustness and reliability of the proposed works performance.