Automatic Energy-Minimised HW/SW Partitioning for FPGA-Accelerated MPSoCs

Field-Programmable Gate Arrays (FPGAs) are known to increase performance and energy efficiency of parallel applications. Integrated on multi-processor systems-on-chip, they can be used as accelerators in addition to the multi-core processor. However, state-of-the-art high-level synthesis tools require an intensive manual effort to make effective use of all available FPGA resources. This letter proposes an automatic HW/SW partitioning software tool which optimises for different design goals, such as performance and power. A given source code is analysed and all necessary decisions and annotations are performed without the need for designer interaction. Further, abstract but accurate power models for FPGA and processor enable power or energy driven optimisation. The tool flow is tested against representative benchmarks on the Xilinx Zynq UltraScale+. On average, an energy reduction of 71% is possible compared to a non-partitioned, sequential execution.