A 2.6 GS/s 8-Bit Time-Interleaved SAR ADC in 55 nm CMOS Technology

This paper presents an eight-channel time-interleaved (TI) 2.6 GS/s 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) prototype in a 55-nm complementary metal-oxide-semiconductor (CMOS) process. The channel-selection-embedded bootstrap switch is adopted to perform sampling times synchronization using the full-speed master clock to suppress the time skew between channels. Based on the segmented pre-quantization and bypass switching scheme, double alternate comparators clocked asynchronously with background offset calibration are utilized in sub-channel SAR ADC to achieve high speed and low power. Measurement results show that the signal-to-noise-and-distortion ratio (SNDR) of the ADC is above 38.2 dB up to 500 MHz input frequency and above 31.8 dB across the entire first Nyquist zone. The differential non-linearity (DNL) and integral non-linearity (INL) are +0.93/-0.85 LSB and +0.71/-0.91 LSB, respectively. The ADC consumes 60 mW from a 1.2 V supply, occupies an area of 400 mu m x 550 mu m, and exhibits a figure-of-merit (FoM) of 348 fJ/conversion-step.