Logic Locking with Provable Security Against Power Analysis Attacks

Outsourcing of integrated circuit (IC) fabrication to external foundries has lead to many new security vulnerabilities including IC piracy, overbuilding and reverse engineering. In this regard, logic locking (LL) was introduced to protect intellectual property (IP) from such threats. In this paper, we evaluate the strength of various logic locking techniques, including earlier works, such as random logic locking (RLL) and fault analysis-based logic locking (FLL), against power-based side-channel attack. We have developed attacks where at least 60% of the key bits can be successfully recovered for 60% of the circuits for both RLL and FLL using a 32-bit key. However, the success rate reduces to 45% and 35% for RLL and FLL, respectively, when using a 64-bit key. We demonstrate the practicality of our proposed attack by mounting it against RLL and FLL implementations of ISCAS’85 and MCNC benchmark circuits on Spartan-6 FPGA platform. Further, we present DPA results on mutual information analysis (MIA) on logic locking techniques that capture any dependence between intermediate data and the captured power traces. We also formally establish that resilience to SAT attack implies resilience to DPA attack as well for a logic locking technique. We validate this further via experiments on Spartan-6 FPGA on SAKURA-G development board for a recent logic locking technique that is known to thwart the SAT attack.