Improving Performance, Power, And Area By Optimizing Gear Ratio Of Gate-Metal Pitches In Sub-10nm Node Cmos Designs

This paper presents improvements in performance, power, and area (PPA) obtained by optimizing the gear ratio (GR) between the Gate and vertical metal layer pitches in standard cells in sub-10nm node CMOS SoC designs. Changing the GR from 1: 1 to 3: 2 leads to better pin accessibility, routability, and higher cell density. This in turn enables a gate pitch relaxation and associated improvements in cell delay. Implementation of 3: 2 GR ultra-dense cells in an SoC CPU block results in up to 17% higher performance, 4% smaller logic size, and 8% lower dynamic power at typical PVT conditions.