The Chess-2 Prototype In Ams 0.35 Mu M Process: A High Voltage Cmos Monolithic Sensor For Atlas Upgrade

CHESS-2 (CMOS HV Evaluation for Strip Sensors) is a novel ASIC strip architecture designed to investigate the feasibility of using HV-CMOS MAPS (Monolithic Active Pixel Sensors) as alternative sensors for the ATLAS Phase-II Strip Tracker Upgrade. The ASIC is optimized for signal processing, hit pixel position encoding and readout. CHESS-2 includes three independent groups of 128 strips composed of 32 pixels each. The pixel includes a charge sensitive amplifier and the first stage of a comparator inside the collecting well. The second stage, the configuration, the encoding and the readout sections are placed at the periphery of the strips. A novel "fast skip" hit encoding logic identifies the first 8 hit pixel positions with a single-bunch time resolution (25 ns) and sends the data to a fast readout circuitry for serialization and transmission on 14 LVDS channels at 320 MHz. Several substrate resistivity variants have been fabricated for a full characterization of the performance aspects.