An Overview of Digital-Intensive Delta Sigma Phase-Locked Loops Utilizing 1-Bit Conversion and Modulation

The digital phase-locked loop (DPLL) enables robust clock generation with advanced CMOS technology but suffers from nonlinearity and resolution problems of the time-to-digital converter (TDC). In the DPLL based two-point modulator, the nonlinearity of the digitally-controlled oscillator (DCO) is also critical. DPLL architectures that utilize a 1-bit conversion or a 1-bit Delta Sigma modulation method are recently proposed to relax the nonlinearity problem. This paper discusses TDC design issues and gives an overview of some useful techniques in the design of the DPLL which performs clock/frequency generation and modulation with the 1-bit TDC or the 1-bit DCO modulation.