Frequency and Voltage Dependence of Interface States and Series Resistance in Ti/Au/p-Si Diodes with 100 μ m and 200 μ m Diameter Fabricated by Photolithography

Ti/Au/p-Si diodes with the diameters of 100 and 200 μ m were fabricated by photolithographic technique. Capacitance–voltage (C–V) and conductance–voltage (G/w–V) characteristics of these diodes have been investigated by considering the series resistance (R s ) and interface states (N ss ) effects. Experimental results show that the value of C and G/w in per area, with D 1 (100 μ m) is lower than that of D 2 (200 μ m) in depletion region but this behavior become reverse at accumulation region. Such behavior of C and G/w can be attributed to the special distribution of N ss at metal/semiconductor (M/S) interface, series resistance (R s ) of diode. The interface states density of the devices determined from high-low capacitance methods are presented for comparison. The voltage dependent profile of R s was obtained for 100 kHz and 1 MHz. The observed anomalous peaks in C–V plots at 100 kHz were attributed to the effects of R s , N ss and native interfacial layer. Experimental result show that the localizations of N ss at Ti/Au/p-Si interface, R s and native interfacial layer have significant effects on the C–V and G/w–V characteristics of Ti/Au/p-Si diodes.