Multiple Patterning Layout Compliance with Minimizing Topology Disturbance and Polygon Displacement.

Multiple patterning lithography (MPL) divides a layout into several masks and manufactures them by a series of exposure and etching steps. As technology advances, MPL is still indispensable because of its cost effectiveness and hybrid lithography capability. Producing a layout by MPL relies on layout decomposition and layout compliance. The former reports conflicts (i.e., identifies undecomposable polygons), and the latter further modifies the layout to clean conflicts. As long as a layout has unresolved conflicts, it cannot be manufactured by MPL. Hence, layout compliance is crucial for MPL. This task, however, becomes more complicated and challenging because of more masks used and design rule explosion at advanced technology nodes. Semi-automation or manual fixing is thus no longer applicable. Moreover, from a designer's perspective, layout modification is desired to preserve interconnect correctness, not to create new conflicts, and to minimize topology disturbance and polygon displacement. Therefore, in this paper, we propose the first fully automatic approach for multiple patterning layout compliance. For achieving this goal, we extract topology relations of polygons and model the layout correction as a polygon legalization problem. Experimental results demonstrate the superior efficiency and effectiveness of our approach. With topology awareness, our spacing constraint handling is general and can be applied to other layout fixing problems.