A Side-Channel Attack Resistant AES with 500Mbps, 1.92pJ/Bit PVT Variation Tolerant True Random Number Generator

In this paper a side-channel-attack resistant AES system with a variation-tolerant true Random Number Generator (tRNG) is implemented using IBM 0.13μm CMOS technology. As the random source for the AES, a meta-stability based tRNG takes advantage of an all-digital self-calibration method to compensate Process-Voltage-Temperature (PVT) variations, and thus guarantees output with extremely high randomness. To quantify performance of the proposed tRNG, NIST tests along with other specification measures are performed. The results show improvements over previous work in bit rate, energy efficiency, and pattern randomness. The proposed AES adopts a rotating S-boxes masking technique to gain high resistance against first and zero-offset second order side channel attacks, including Differential Power Analysis (DPA). The masked AES is simulated under first order and zero-offset second order DPA, showing significant resistance against these attacks.