Qualification of 3D integrated silicon photonics

Recent progress made in Silicon Photonics building blocks has paved the way for large scale industrialisation of devices that can be fabricated in existing CMOS fabs, and recently important steps have also been taken on the industrialisation on 12" wafers. In this paper we outline the industrialisation of the assembly and test processes required to enable the implementation of Silicon Photonics including the use of 3D face to-face integration of separate electronics and photonics die. We pay particular attention to the qualification procedure of the 3D integrated die, including all the various tests passed during the qualification process. Details are given of the test package used during the 3D qualification used with Thermo-mechanical simulations of the test package.