Scheduling Data in Neural Network Applications.

FPGA(2019)

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摘要
Neuromorphic computing is becoming common in diverse systems, including time-sensitive, real-time systems. This requires that large data sets be processed quickly with low latency. A stream processing architecture helps achieve this goal by beginning processing as soon as samples are received. In this paper, to achieve a low-latency implementation, neurons are parsed into fine-grain operations and scheduled onto stages of the pipeline. Wide datapaths that process multiple samples in each stage of the pipeline greatly improve throughput and latency. Also, the sparsity of partially connected neural networks allows proposed schedulers to further decrease latency. These schedulers use 'greedy' heuristics based on data dependencies to develop a reduced latency schedule. The schedulers were testing against sets of 1000 partially-connected neural networks, with sets ranging in number of layers from three to fifteen. The set of heuristics developed showed reductions of up to 67% over a sequential schedule.
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