Accelerating Reconfiguration For Vlsi Arrays With A-Star Algorithm

We describe a novel technique to speed up the reconfiguration for the very large scale integration (VLSI) arrays. We propose an efficient algorithm, making use of the idea of the A-star algorithm, for accelerating the reconfiguration of the VLSI processor arrays to meet the real-time constraints of embedded systems. The proposed algorithm treats the problem of constructing a local optimal logical column that has the minimum number of long interconnects as a shortest path problem. Then the local optimal column can be constructed by utilizing the A-star algorithm with the appropriate heuristic strategy. We prove that the proposed method can find the shortest local logical column. Simulation experiments reveal that the proposed algorithm can greatly reduce the number of visits to the fault-free processing elements (PEs) for constructing a local optimal logical column and effectively decrease the reconfiguration running time. Experimental results show that the computation time can be reduced by more than 38.64% for a 128x128 host array with fault density of 20%, without loss of harvest. (c) 2018 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.