A 28 GHz four-channel phased-array transceiver in 65-nm CMOS technology for 5G applications

A Fully integrated 4-element symmetrical TX/RX RF integrated circuit for 26–30 GHz 5G beam-forming system is implemented in 65-nm CMOS technology. Each array element is digitally controlled with 5.625° step and 2 dB gain step. The system employs a heterodyne architecture with 6 GHz intermediate frequency (IF). The up-conversion and down-conversion mixers are integrated on the same chip with a shared LO driver chain. The phased-array power combining/splitting is done using Wilkinson combiner/divider. The RFIC features 3.4 to 3.9 dB noise figure and −5 to −3.5 dBm IIP3 in RX mode, 18 dB maximum power gain and OP1dB of 14.7 dBm per chain in TX mode. The maximum root mean square amplitude and phase error of each array element is 0.25 dB and 1.5°, respectively. The RFIC area is 18 mm ² including pads and it consumes 240 mW per TX chain, 120 mW per RX chain and 174 mW for the LO amplifier with total power of 1.58 W from a 1.2 V supply.