Energy efficient QCA circuits design: simulating and analyzing partially reversible pipelines

Energy efficiency is an important issue to consider when it comes to digital systems development. Despite all the accomplishments in CMOS evolution, there has been an active search for its replacement. Although most of these emerging technologies present very low power consumption, they are energetically bounded by a hard thermodynamic limit. In an attempt to help design systems capable of going beyond the limit aforementioned, we focus on embedding a new clocking scheme in the main CAD tool for quantum-dot cellular automata. More specifically, we implemented the Bennett clocking scheme and a partially reversible pipeline in the QCADesigner software simulator. We also carried out an energy-throughput analysis for the state-of-the-art benchmark combinational suite. Our results, compared to the conventional clock, show that in 60% of the circuits, the energy improvement surpasses the throughput degradation for the best energy configuration. When throughput is a concern, the designer has on average 15 different configurations for each of these benchmark circuits that can be traded trade between these metrics. To the best of our knowledge, this work presents the first attempt to add reversible features in the main CAD tool for QCA systems design and show an analysis of viable clock configurations for the circuits mentioned above. These efforts open new perspectives in designing QCA systems where energy efficiency is mandatory.