Junction isolated MOS/LDMOS cascode arrangement for radiation tolerant RF-power applications

Mixed signal on chip solutions for space applications and high energy physics experiments require high voltage RF-LDMOS transistors with a sufficient ruggedness against ionizing radiation and single event burn out effects. We report on the effectiveness of a novel hardening by design approach for radiation tolerant integrated RF power MOSFET transistors confirmed by single event burn out (SEB) and total ionizing dose (TID) radiation tests. In order to substantially decrease the TID related leakage currents the lateral shallow trench isolation (STI) was replaced by narrow junction isolation regions. To significantly increase the onset voltage for SEB events of LDMOS transistors a MOS/LDMOS cascode arrangement has proven as a suitable approach. The common floating MOS drain/LDMOS source node of the cascode arrangement is permanently reverse biased, so that the turning on of the LDMOS parasitic bipolar transistor is suppressed. The properties of the Junction Isolated Cascode LDMOS with respect to area consumption, DC and RF performance and ruggedness against malfunctions due to TID and SEB effects were verified by comparison with standard trench isolated NLDMOS and junction isolated NLDMOS devices. The junction isolated NMOS/NLDMOS Cascode features a break down voltage BVDS > 40V a maximum cut off frequency f _T =15 GHz and a maximum oscillation frequency f _MAX = 25 GHz. In comparison with standard NLDMOS the laterally junction isolated NMOS/NLDMOS Cascode device shows an increase of the SEB onset voltage from 14V to 24V at a linear energy transfer LET of 67.7 MeVcm ² /mg and negligible source drain leakage currents up to a TID of 1.5 Mrad after irradiation with a 60Co source.