Paralleling 650 V/ 60 A GaN HEMTs for high power high efficiency applications

In this paper, the design and operation of two 650 V/60 A Gallium Nitride (GaN) devices in parallel is discussed in detail, further, the challenges faced and the trade-offs required for paralleling high speed GaN devices are also examined. The dynamic characterization of two devices in parallel is presented in detail. The phase leg design requires both power loops and gate loops to be as small and as identical as possible for the two devices as for high speed GaN devices, even a small parasitic inductance or capacitance added due to the layout causes high overshoot in device voltage and current. The Double pulse tester (DPTer) design required for dynamic characterization of devices in parallel is slightly different from the phase leg design. Each device current is measured separately using a current shunt connected in series with the device. The shunts also add parasitic inductances in series with each device which limits the performance of the DPTer. Dynamic characterization performed includes characterization of a single device till 400 V, 60 A which then goes on to discuss characterization for paralleled devices. The major challenge faced in paralleling is the issue of circulating current between the two devices during turn-on transient which is discussed in detail, its causes and ways to mitigate the circulating current are also presented. This paper also examines two designs-the first one is the recommended design from GaN System([1]) which uses the same split off-state and split on-state gate resistors, thus using only one resistor to control circulating current, turn-off speed and the Miller effect. The second design presented is the improved version of the recommended design which has completely different split on state and split off-state gate resistors, thus using different gate resistors to control circulating current and turn-off speed. The performance of both the designs is compared from Double Pulse Test (DPT) results.