How to build a Generic Model of complete ICs for system ESD and electrical stress simulation?

For precise system ESD simulation the transient chip behavior needs to be modeled accurately. As there are several typical characteristics possible (e.g. diode breakdown, snapback-element or forward diode) a straight forward methodology to build a generic model for transient behavior with destruction limits in SPICE is presented. This enables full-system transient ESD and electrical stress simulation for system robustness evaluation.