Split-transistor compensation: Application to a low-dropout voltage regulator (LDO)

A controlled comparison of three compensation techniques - nested Miller compensation (NMC), Split-Length compensation (SLC) and the new Split-Transistor compensation (STC) - is performed in a multi-stage low-dropout voltage regulator (LDO). The LDO with STC used 41% and 84% lower total compensation capacitance compared to the LDOs with SLC and NMC, respectively. To verify the proposed compensation technique, a micro-power LDO using STC has been fabricated in a 0.5-mu m CMOS process. Experimental results show an undershoot of 126 mV for a 1 mu A - 50 mA load step and an overshoot of 556 mV for a 50 mA - 1 mu A load step. At a total quiescent current of less than 5 mu A, the fabricated micro-power LDO with STC finds application in IoT devices.