Tunneling Mosfet Technologies Using Iii-V/Ge Materials

The critical issues, technical challenges and viable technologies of tunneling MOSFETs (TFET) utilizing III-V/Ge materials are examined in this study. N-channel TFETs using InGaAs bulk and quantum well (QW) homojunctions, GaAsSb/InGaAs type-II hetero-junctions and Ge/strained SOT type-II hetero-junction are fabricated with emphasis on the superior source p(+)/n junction formation and the electrical properties are experimentally evaluated. It is found that InGaAs/In0.7Ga0.3As(3nm)/InGaAs QW n-TFETs with W/HfO2/Al(2)O3 gate stacks (CET of 1.4 nm) exhibit the minimum sub-threshold swing (S.S.(min)) of 55 mV/dec. at room temperature, thanks to the steep-profile and defect-less Zn diffused p(+)/n source. Also, C-doped p(+) GaSb/InAs and C-doped p(+) GaAsSb/InGaAs n-TFETs on Si substrates are realized by employing direct wafer bonding. In addition, in-situ B-doped Ge/strained-Si hetero-junction TFETs are presented. P+ Ge/SOI n-TFETs with 1.1% bi-axial tensile strain exhibit steep S.S.(min) below 30 mV/dec. and large I-on/I-off over 10(7).