Custom 16-channel, 12-bit, 500MHz ADC module for the KOTO experiment at J-PARC

This paper presents a 16-Channel, 12-Bit, 500 MHz ADC/Data Processing Module, designed for the KOTO Experiment at the Japan Proton Accelerator Research Complex (J-PARC). Few hundreds of this 6U VME board will receive signals from various detectors of the apparatus, and will be the digitizing modules in the Experiment's Data Acquisition System (DAQ). In KOTO, the main ADC/DAQ system runs at a 125 MHz simultaneous sampling rate, provided by one low jitter system clock. The 500 MHz ADC Module receives this system clock and multiplies its frequency by four with an internal PLL. The 16 analog input pulses are passed to 8 dual channel ADC chips (ADS5407). After sampling, data are processed locally with two Field Programmable Gate Arrays (FPGA). The module is equipped with a pipeline up to 40us (20,480 samples) long, where digitized values are stored, awaiting the system Level 1 trigger. After the trigger, data are packed and buffered for readout. The readout can be performed via the VME32/64 backplane, or via the two front panel QSFPs at rates of up to 48Gbps. Designed specifically for the KOTO Experiment, this module can also be used in many other Physics applications. The design and preliminary test results will be described.