Probe Card Design with Signal and Power Integrity for Wafer-Level Application Processor Test in LPDDR Channel

In this paper, a vertical probe card design for wafer-level mobile application processor (AP) chip test is proposed under LPDDR4 channel specifications. The probe card consists of a probe head and a multi-layer ceramic (MLC) board, and it is designed to have signal and power integrity to guarantee the wafer-level AP chips to be operated at 3.2 Gbps of speed under 1.1 V of supply voltage. We proposed insertion of additional ground cobra-shaped needles insertion in the probe head to reduce crosstalk noise and secure return current path. In the far-end crosstalk (FEXT) noise simulation and eye-diagram simulation, FEXT noise in the proposed probe head is suppressed 20 dB at 1.6 GHz, and the eye-open size is increased from 17.9 % to 83.3 % at 1.6 Gbps of speed. Measurements are also conducted and well correlated with the simulation results. In MLC board design, over 500 number of 1 uF decoupling capacitors are implemented on the top layer and the bottom side of the board to lower power distribution network (PDN) impedance. In addition, some power planes for LPDDR memory power supplies are repositioned to upper layers of the board. The PDN impedance curves of the memory power domains are lowered by nearly 20 dB at frequencies above the GHz range. To validate the proposed methods, the original and the revised probe card are compared in the frequency-and time-domain simulations. S-parameters of the probe head are extracted from 3-D EM simulation, and those of the MLC board are extracted from SIwave simulation. For exact eye-diagram simulations, eye-mask information and various conditions of LPDDR4 channel are referred to JEDEC standard.