On gate function based tests for scan designs

Recently we proposed generation of tests for scan designs based on the functions of gates used in the designs. The tests for gates used in the design were derived based on minimal true and maximal false vertices of the functions realized by the gates. Next tests for gates in the design are generated by a modified ATPG that attempts to embed the gate tests in to tests for the scan designs using the gates. Often not all derived gate tests could be embedded in to scan tests due to the constraints imposed by the gate tests. In this paper we propose using what we refer to as exclusive cubes as gate tests. These gate tests are more flexible than the gate tests using minimal true and maximal false vertices. The added flexibility facilitates embedding gate tests in to scan tests. We provide experimental results on larger ISCAS-89 and ITC-99 benchmark circuits to demonstrate the effectiveness of using exclusive cubes in generating scan tests for designs using complex gates.