Primary single event effect studies on Xilinx 28-nm System-on-Chip (SoC)

Single Event Effect (SEE) on Xilinx 28-nm System-on-Chip (SoC) was investigated by both simulation and experiments in this study. In the simulation process, typical structure of NAND gate and flip-flop in SoC were designed using Cadence tool. Various kinds of radiation were simulated as pulsed current source in consideration of multilayer wiring and energy loss before reaching the sensitive area. The circuit modules were simulated as SEE occurred and malfunctioned when pulsed current source existed. The changes of the circuit modules output were observed when pulsed current signals were placed at different sensitive nodes or the circuit operated under different conditions. The sensitive nodes in typical modules and the possible reasons of test program malfunction were primarily studied. In the experimental process, SoC chip was irradiated with α particles, protons and laser respectively. The irradiation test results showed that Single Event Upset (SEU) occurred in typical modules of SoC, in accordance with the simulation results.