Using Runtime Circuit Specialization to Accelerate Simulations of Reconfigurable Architectures

Hardware simulations are never fast enough, and simulations of reconfigurable architectures are especially slow. The problem is that the programmable switching network that takes up most of the area in a reconfigurable architecture is not handled well by modern RTL simulators. In this paper we describe the design of a new RTL simulator that uses runtime circuit specialization (RCS) to solve this problem. Our simulator works by compiling a specialized version of the architecture being simulated after the configuration being tested has been loaded. To use our method an engineer adds small hints about what to specialize to the testbench. The RTL description of the chip being tested does not need to be changed. To test our simulator we use it to accelerate regression tests of an island style CGRA designed for use in image processing. Long testbenches of this design are up to 6x faster in our simulator than in state-of-the-art commercial simulators. We believe that runtime circuit specialization could produce similar speedups in simulations of other reconfigurable chips as well.