A Low Power All-Digital PLL With -40dBc In-Band Fractional Spur Suppression for NB-IoT Applications.

This paper proposes a low-power fractional-N all-digital PLL (ADPLL) for the narrow-band Internet-of-Things applications. Multi-step lock controlling and oscillator tuning word coarse prediction algorithms help to accelerate the locking process to less than 20 mu s. A digital-to-time converter (DTC) is used with a phase prediction algorithm to minimize the detection range of the time-to-digital converter for low power consumption. The Sigma Delta dither block is designed to improve the nonlinearity of DTC resulting in a -40-dBc in-band spur suppression. A low supply of 0.6-V digitally controlled oscillator has the frequency coverage of 1.5-2.05 GHz. Fabricated in a 55-nm CMOS, the ADPLL occupies an active area of 0.88 mm(2) and consumes 4 mW at 1.8 GHz. With a 24-MHz reference clock, the measurement results show that this work achieves better than -94-dBc/Hz in-band phase noise and -120.5 dBc/Hz at 1-MHz offset of 1.83-GHz carrier frequency. The FoM value is -233.4 dB, and the reference spur is -76.3 dBc.