Cost-efficient 3D Integration to Hinder Reverse Engineering During and After Manufacturing

Reverse engineering (RE) attacks pose a serious threat to the semiconductor supply chain. In this paper, we address this problem by proposing a design flow that leverages the unique capabilities of 3D integration to synergistically combine split fabrication and circuit camouflaging. First, 3D heterogeneous multi-chip integration is utilized to support efficient dielevel split fabrication to protect against RE during manufacturing. Second, to prevent RE after manufacturing, a subset of the trusted foundry's die is obscured to significantly increase decamouflaging difficulty. A security-based cutsize-optimized partition algorithm is proposed to maximize the number of securely camouflaged gates on the trusted die while reducing the cutsize. Third, cost modeling is applied to demonstrate the cost effectiveness of the proposed 3D split fabrication flow compared with existing solutions. Across six widely used benchmarks, evaluations on 3D split fabrication designs between 15nm to 90nm processes show that the proposed design can effectively hinder practical RE attacks during manufacturing (Hamming Distance=30%) and after manufacturing (Complexity-to-Decamouflage=145), with minimum overheads to cutsize, foot-print, and cost.