Design of Crystal-Oscillator Frequency Quadrupler for Low-Jitter Clock Multipliers
IEEE Journal of Solid-State Circuits(2019)
摘要
Implementation of low-noise power-efficient clock multipliers requires low-noise high-frequency reference clocks. This paper presents ways to generate such reference clocks at four times the frequency of a standard crystal oscillator (XO) output frequency. Using extensive digital correction techniques, a 216-MHz reference clock with an integrated jitter of 77
$\text {fs}_{\mathrm{ rms}}$
is generated from a 54-MHz Pierce XO. A ring oscillator-based injection locking clock multiplier driven by the proposed quadrupler is used to demonstrate the efficacy of the quadrupler. Fabricated in a 65-nm CMOS process, the proposed clock multiplier occupies an active area of 0.16 mm
2
and achieves 366
$\text {fs}_{\mathrm{ rms}}$
integrated jitter at 4.752-GHz output frequency while consuming 6.5-mW power from a 1.0-V supply of which 1.5 mW is consumed in the quadrupler.
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关键词
Clocks,Jitter,Phase locked loops,Resonant frequency,Voltage-controlled oscillators,Crystals,Delays
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