A SAT-based Timing Driven Place and Route Flow for Critical Soft IP

Many FPGA designs contain soft IP tightly connected to hard blocks such as on-chip Processor, PCIE or IOs. Generally, these soft IPs pose significant timing closure challenges. In this paper, we propose a timing-driven Place and Route flow based on Boolean Satisfiability (SAT). Its main advantages over previous SAT-based approaches are its improved scalability and its timing awareness. We validate our flow using an IP targeting the emulation market. We demonstrate that our flow can significantly improve the usable bandwidth of FPGA IOs. Since the proposed flow is SAT based, the performance does not depend on specific ways in which more traditional place and route are usually tuned.