A High-Speed Realization Of The Delayed Dual Sign Lms Algorithm

Motivated by reduction of computational complexity and improvement of convergence speed, this work develops a high-speed VLSI realization of the adaptive FIR filter based on the delayed dual sign LMS (DDSLMS) algorithm. Not only is the computation of the proposed algorithm the same as that of the sign LMS algorithm, but also the convergence characteristic is close to that of the LMS algorithm. The fine-grained dot-product unit and multiple-input-addition unit are adopted to reduce the latency of critical path. From the ASIC synthesis results we find that the proposed architecture of an 8-tap filter has nearly 38% less power and nearly 43% less area-delay-product (ADP) than the best existing structure.