A continuous-time delta-sigma modulator with self-ELD compensated quantizer

A new excess loop delay (ELD) compensation technique, called self-ELD compensation, is proposed in this paper. The digital output information is stored on the input parasitic capacitance of a comparator and used to perform ELD compensation. No dedicated ELD compensation circuit, such as opamp or digital-to-analog converter (DAC), is required, since the proposed method uses the existing circuit component for the ELD compensation. The non-linear parasitic capacitance is linearized by maintaining the input transistor pair always in one region of operation. As a proof of concept, a 3 ^rd order continuous-time delta-sigma modulator with the proposed self-ELD compensation is fabricated in a 0.13 μm CMOS process with an active area of 0.1 mm ² . The prototype ADC operates at 500 MHz sampling frequency, and achieves a peak SNDR of 74.4 dB and a peak SNR of 76.2 dB in a 15 MHz bandwidth while consuming 10.1 mW from 1.2 V supply.