A High Efficiency and Fast Transient Digital Low-Dropout Regulator With the Burst Mode Corresponding to the Power-Saving Modes of DC–DC Switching Converters

2018 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE - (ISSCC)(2020)

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摘要
The proposed digital low-dropout regulator uses nonlinear switching control (NLSC) technique to suppress voltage ripple to less than 6 mV when the switching noise voltage of a switching regulator operating in a power-saving mode is greater than 50 mV. In addition, the NLSC technique improves the current efficiency by reducing the quiescent current to less than 10 μ A and reduces the switching power loss through variable switching frequency control. With a load step of 1–20 mA, the transient response time is 1.3 μ s and the peak current efficiency is 99.8% at heavy loads.
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关键词
power-saving modes,voltage ripple,DLDO techniques,switching frequency,power switches,nonlinear switch control technique,burst mode technique,normal freeze modes,power reduction,freeze mode,diode emulation mode,pulse frequency mode,high-efficiency DC-DC switching regulator,integrated power management,DC-DC switching converters,fast-transient digital-low-dropout regulator
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