A 13mW 64dB SNDR 280MS/s pipelined ADC using linearized open-loop class-AB amplifiers.

A 12bit pipelined ADC based on a class-AB open-loop integrator as residue amplifier is presented. The integrator uses an analog linearization scheme by tuning opposing distortion mechanisms to cancel each other. The gain errors and non-linearity are detected in background with the help of split-ADC calibration technique. The mismatch between the two split-ADCs is minimized by sharing the residue amplifier and adding the offset sequentially. The prototype ADC, implemented in 28nm CMOS, achieves 64dB SNDR and 77dB SFDR after calibration. Operating at 280MS/s, the ADC consumes 13mW, exhibiting a Walden FoM of 35.8fJ/conv.