Fine-grained 3D reconfigurable computing fabric with RRAM

Non-volatile 3D FPGA research to date utilizes layer-by-layer stacking of 2D CMOS / RRAM circuits. On the other hand, vertically-composed 3D FPGA that integrates CMOS and RRAM circuits has eluded us, owing to the difficult requirement of highly customized regional doping and material insertion in 3D to build and route complementary p- and n-type transistors as well as resistive switches. In the layer-by-layer non-volatile 3D FPGA, the connectivity between the monolithically stacked RRAMs and underlying CMOS circuits is likely to be limited and lead to large parasitic RCs. In this paper, we propose a fine-grained 3D reconfigurable computing fabric concept. It implements CMOS / RRAM hybrid circuits within the pre-doped vertical nanowire template. Transistors and resistive switches can be integrated with fine granularity, which reduces the routing overhead between RRAM and CMOS circuits and increases the density. We estimate the density benefit of the proposed fabric to be 27X relative to the monolithic 3D FPGA with stacked RRAMs. Estimated Elmore delays are improved by 5.4X and 2.2X for configuration and normal operation, respectively.