A 1.1-mW 10-bit 50-MSample/s hybrid two-step ADC in 0.13-µm CMOS technology

This paper presents a hybrid two-step analog-to-digital converter (ADC) that employs a successive approximation register (SAR) ADC and a time-to-digital converter (TDC)-based ADC as coarse and fine converters, respectively. By exploiting the respective advantages of the SAR and TDC architectures, the two-step ADC is realized without a high-gain amplifier for high linearity of a multiplying digital-to-analog converter. Thus, the proposed architecture can implement a low-power ADC without compromising operational speed. In addition, two digital error corrections are used to compensate for TDC error and the final ADC output, respectively. A 10-bit 50 MS/s ADC is fabricated in a 0.13-μm complementary metal–oxide–semiconductor process and occupies a 0.12-mm 2 die area. Furthermore, it consumes only 1.1 mW and achieves a signal-to-noise distortion ratio and spurious-free dynamic range of 53.67 and 60 dB, respectively, resulting in a 53.7 fJ/conversion-step at a 25-MHz full-scale input.