Reducing The Energy Of A Large Hybrid Cache

Energy is quickly becoming an inevitable challenge to using a large die-stacking DRAM cache. Emerging STT-RAM technology can efficiently reduce the static energy of large cache. However, STT-RAM which has high write energy and latency is not suitable to completely substitute for on-die DRAM cache. We observe that there are a large number of redundant bits written in the row buffer and futile bits written back to STT-RAM cells, which do not actually change the cells' value but still cost write energy. We utilize this opportunity to reduce energy by removing the unnecessary bit-writes to the STT-RAM cache. In this paper, we design a large hybrid cache architecture with a DRAM region and STT-RAM region. Selective Write Back to Row Buffer and Selective Write Back to Cell Array optimizations are proposed to reduce high write energy of STT-RAM region by comparing write data and existing data in advance. Also, we propose Reuse Distance Oriented Data Movement to reduce write operations in STT-RAM region. The results show our hybrid cache can achieve up to a 28.3% energy reduction and 6.7% performance improvement.