A Digital Low-Dropout-Regulator With Steady-State Load Current (Slc) Estimator And Dynamic Gain Scaling (Dgs) Control

conventional digital low dropout (D-LDO) regulator usually suffers from the drawback of long settling time during transient response due to the usage of shift register architecture. In this paper, the proposed D-LDO regulator can observe the output voltage variations during load transient time to predict the load current for fast transient response. Near optimum turn on power MOSFET in steady state can be derived by the proposed steady-state load current (SLC) estimator while the dynamic gain scaling (DGS) technique can improve transient response and avoid limiting cycle oscillation (LCO) problem. Test chip was designed in 0.18 mu m CMOS process. Simulation results showed the transient response time can be reduced by 88% from 920ns to 115ns.