Securing Test Infrastructure Of System-On-Chips

The rapid development in the modern technology and its widespread utilization in number of applications brings in new challenges that need to be addressed. Security is one of such challenges that has grown into a major concern over the years. Periodically new incidents of data and system breaches are reported. For this purpose, usually different side channels in the system are being exploited by the attackers to bypass the protection mechanisms. Especially vulnerable with this regard is the traditional test and debug infrastructure placed on the System on Chips (SoC) which provides an alternative path into the chip internal structure. The aim of this paper is to present a comprehensive overview of various security aspects of SoCs including the known threat models, classification of attackers and existing techniques as well as present the solution concept for secure SoC Test Infrastructure with the focus on embedded cores testing.