Leakage current analysis in static CMOS logic gates for a transistor network design approach

This work evaluates the static power component of static CMOS logic gates. Simulations at the electrical level (SPICE) were performed to evaluate the transistors stacking effect on different manufacturing processes using a group of logic gates. The transistors stacking effect was selected because it can be easily incorporated into a transistor network design or library-free approach that has also shown improvements in terms of leakage current reduction. Predictive technology models (PTM) were used ranging from 130 nm to 32 nm. The influence of the temperature over the stacking effect was also evaluated. The results show that the stacking effect is highly sensitive to the input vector of the logic gate, obtaining variations up to 232 times in the total leakage current. The effect of the stacking technique is reduced when the stacked transistors are activated. Additionally, the effect of this technique on the gate leakage current was also evaluated, because is one of the three principal components of the leakage current and is increasing in the last fabrication technologies. The results show that the gate leakage current is not reduced by the stacking effect, but it is influenced by the topology of the logic function. The gates with NAND topology (NMOS transistors in series) have less gate leakage current than the gates with NOR topology (PMOS transistors in series).