A 400mV active VMIN, 200mV retention VMIN, 2.8 GHz 64Kb SRAM with a 0.09 um2 6T bitcell in a 16nm FinFET CMOS process.

We propose and demonstrate in silicon simple, new circuit solutions using a standard 1-1-2 fin 0.09 um(2) 6T SRAM commercial bitcell in a 16nm FinFET CMOS process to enable a 400mV active VMIN, 200mV retention VMIN SRAM in a 64Kb CMOS array with 128b/BL. Active VMIN is enabled with a self-triggered feedback on an under-driven BL with faster and more robust signal development on the BL at lower voltages - providing dual read assist, and also a 2X tighter offset voltage distribution when compared to conventional differential voltage sensing. 200mV retention VMIN is enabled by reusing write assist circuit overhead while engaging two key observations: insensitivity of bitcell stability to systematic variations and sensitivity of bitcell data to noise on the power grid in the subthreshold/near threshold region. Average FMAX of 140MHz and 2.8GHz are measured across all chips for VDD at 0.4V and 0.9V respectively.