Behavioral Emulation For Scalable Design-Space Exploration Of Algorithms And Architectures

This paper presents a simulation methodology called Behavioral Emulation (BE) for scalable design-space exploration of algorithms and architectures. By design, BE is independent of simulation vehicle (e.g., simulation in software or emulation in hardware) and addresses system-simulation complexity with a coarse-grained, multi-scale approach. We describe the BE methodology, component models, and simulation workflow from calibration to validation of applications simulated on existing architectures and present a device-level case study with roughly 10% relative error. Finally, we discuss the extension of validated models to predict application performance on notional architectures.