A 1.2–5Gb/s 1.4–2pJ/b serial link in 22nm CMOS with a direct data-sequencing blind oversampling CDR

Sudip Shekhar,Rajesh Inti,James E. Jaussi,Tzu-Chien Hsueh,Bryan Casper

Symposium on VLSI Circuits-Digest of Papers（2015）

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摘要

A scalable-rate serial link comprising of a bidirectional transmitter (TX)/receiver (RX) and two all-digital PLLs (ADPLLs) operates at 1.2-5Gb/s from 0.55-0.7V DC supply with 1.4-2pJ/b total energy efficiency, respectively. Power efficiency is improved by avoiding the use of any analog circuitry, a low swing voltage-mode transmitter, and a direct data-sequencing blind oversampling (DDS-BOS) clock and data recovery (CDR). Using DDS in feed-forward BOS-CDR obviates area and power consuming FIFOs, improves jitter tolerance (JTOL), and peunits up to 7500ppm frequency tolerance (F TOL) between the TX-RX clocks rendering it attractive for fast-locking continuous/burst operation.

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关键词

CMOS,direct data-sequencing blind oversampling CDR,scalable-rate serial link,bidirectional transmitter/receiver,all-digital PLL,power efficiency,analog circuitry,low swing voltage-mode transmitter,clock and data recovery,jitter tolerance,frequency tolerance,voltage 0.55 V to 0.7 V

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