Characterisation of feasibility regions in FPGAs under adaptive DVFS

Implementing Dynamic Voltage and Frequency Scaling (DVFS) is a non-trivial task on FPGAs and requires knowledge about the feasible voltage and frequency (VF) ranges as a first step. The VF feasible ranges depend not only on the size of the critical path in the design but also on the inter- and intra-die variability on the FPGA die. Moreover, the variations in the configuration of the FPGA highly affect feasible VF ranges. Therefore, it is crucial to characterise feasibility by studying the relationship between feasible VF regions and these sources of variability in FPGAs. In this paper we employ a self-checking multiplier which uses residue codes and DVFS implemented on the programmable logic component of a Xilinx Zynq ZC702 device as an error-detection circuit to study these feasible regions. Results show that, as expected, feasible VF ranges vary with FPGA configuration. More interestingly, significant variation of the feasible VF regions is found for different dies. These results highlight the necessity of dynamic self-testing as a part of an adaptive DVFS implementation on FPGAs. Employing the techniques presented in this work enables the implementation of efficient adaptive on-line DVFS on programmable logic while ensuring reliability.