Design and Simulation of Breaking Time Sequence for DC Circuit Breaker with a Current-Limiting Inductance

It is great significance for development of MTDC (Multi-terminal HVDC) to build DC transmission and distribution grids. However, the relatively low impedance in DC grids makes the fault penetration much faster and deeper. Consequently, fast and reliable DC circuit breaker is needed to isolate faults. Breaking time and other parameters are important for a breaker to achieve its goals. This paper presents a DC circuit breaker with a current-limiting inductance and gets the rising and falling characteristics of fault current. Based on the characteristics, a design method of breaking time sequence will be given, as well as the calculation of current-limiting inductance and the selection principles of arresters. A 10kV DC distribution grid is modeled and simulated by PSCAD/EMTDC to verify that the method can meet the requirements of breaking fault current quickly and reliably.