Device Simulations on Novel High Channel Mobility 4H-SiC Trench MOSFETs and Their Fabrication Processes

The aim of this study is to combine the UMOSFET design with its U-shape trench-gate architecture which is well-established in silicon technology and benefits from a reduction in cell pitch size as well as from the elimination of the junction-FET region with the superior material properties of 4H-SiC. While current planar SiC MOSFET devices are challenged by a high ON-state resistance caused by relatively poor channel mobilities due to different scattering processes at the 4H-SiC/insulator interface, our hybrid approach benefits by the normal carrier injection in the inversion channel formed along the {1120} direction which exhibits a higher channel mobility. In this contribution we focus on special lateral test structures which have a similar architecture as compared to vertical power devices but enable us to exclusively characterize the channel mobility. In vertical power devices however only the total ON-resistance which consists of various different resistance components can be assessed.Numerical simulations on the trench width and the gate insulator thickness have been performed to study their influence on the electronic performance. Furthermore, a brief insight on the dry-etching process of trench structures in 4H-SiC will be given. Display Omitted Transconductance curves of lateral 4H-SiC trench MOSFETs have been simulated.Different trench widths have been compared to a planar device.The influence of the gate insulator thickness on the mobility has been studied.Etch profiles show almost perfect vertical sidewalls without any trenching effects.