Challenges of Scalable 2.5D IC Assembly

Driven by key metrics, including higher computing performance, lower power consumption, smaller form factor, increased bandwidth, and reduced latency (interconnect delay), the semiconductor interconnect technology is transitioning to 2.5D and gaining acceptance in the industry, as an increasing number of products are beginning to enter volume manufacturing. To transition from today's low volumes to high volume manufacturing (HVM), the concerns of warpage control, thermal dissipation, cost (yield and throughput), and overall technology scalability for future generations need to be addressed rapidly. The solutions in these relatively new packaging technologies encompass design/layout, material, process, and integration choices. With these concerns as a backdrop, our article will discuss our approach to optimizing 2.5D assembly for HVM. This article starts with a review of our test vehicle and our overall choices of substrate, interposer, and die dimensions. Three different 2.5D assembly approaches that have been investigated for warpage control, ease of process, and impact on yield and reliability will be discussed in detail. It is our finding that for achieving high yield and reliability, in the design stage of the system detailed considerations must be given to not only the electrical performance and signal integrity but also the thermal and mechanical behavior of the system in operation as well as the entire process history. This article reports our results from critical areas including temporary bonding, thermocompression bonding, mass reflow, thin wafer/die handling, flux, underfill, and molding. This article also presents our understanding of the underlying principles governing the technology bottlenecks in advanced packaging and the three flows will be compared with an assessment of their advantages and disadvantages. In the last portion of this article, recommendations are made for an optimized assembly process flow.