Impact Of Grounding The Bottom Oxide Protection Layer On The Short-Circuit Ruggedness Of 4h-Sic Trench Mosfets

2014 IEEE 26TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & IC'S (ISPSD)(2014)

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摘要
This paper investigates the effects of grounding the ptype gate-oxide protection layer called bottom p-well (BPW) of a trench-gate SiC-MOSFET on the short-circuit ruggedness of the device. The BPW is grounded by forming ground contacts in various cell layouts, and the layout of the contact cells is found to be a significant factor that determines the short-circuit safe operation area (SCSOA) of a device. By grounding the BPW in an optimized cell layout, an SCSOA of over 10 mu s is obtained at room temperature. Further investigation revealed that minimizing the distance between the ground contacts for the BPW is a key to developing a highly-robust, high-performance power device.
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关键词
logic gates,grounding,resistance,earthing,lattices,layout,wide band gap semiconductors
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